Time delay circuits are widely utilized in semiconductor applications. Conventionally, a delay circuit may be based on a complementary metal oxide semiconductor (CMOS) inverter cell 10 as shown in FIG. 1. When the CMOS inverter is operating, a P-type metal oxide semiconductor field effect transistor (MOSFET) 101 or an N-type MOSFET 102 with a load capacitor 104 may comprise a resistor-capacitor loop which has a propagation delay time, and thereby the input signal is delayed. Generally, the delay time of CMOS inverter 10 is not drastically affected by the system power supply voltage Vcc.
However, in certain applications, it is required that the delay time varies with the change of Vcc, thus providing a high power supply rejection ratio for the system. For example, in a synchronous buck controller or converter system, the dead-time of the buck converter increases as Vcc voltage decreases. The reason is that when Vcc reduces, the propagation delay of the adaptive gate driving circuitry increases. Thus a delay circuit with drastically different delay time at low Vcc from that at high Vcc is desired to compensate the system and to optimize the dead-time of the converter system. Although a digitally controlled delay circuit with feedback loop may be utilized to meet the requirement, it also has drawbacks such as high cost, complicated structure and large area occupation.